DMA controler:
At first we have to know what is DMA , DMA stands for Direct Memory Access. It is one of the way to accomplished highspeed data transfer directly between the memory and the periferal device with out the interfere of micrprocessor
Block diagram of 8257 (DMA controller) :
8257is a 4-channel programmable DMA controller used 8085 and other microprocessor for DMA and can effect data transfer between memory and any 4 periferal in BEN and DMA , when a periferal DMA transfer , the 8257 gain control of the system bus and generates a sequencious address, allow it required control signal. Allow periferel to either WRITE data directly into memory or READ data from memory without using microprocessor. The 8257 gains control of system bus by using Microprocessor.
The 4-periferel device connected to DMA control can be assigned priorities fo required number of DMA cycle . The 8257 keeps track of the number of bytes trnsfer for each channel and issue.
Interfacing DMA controller with microprocessor:
(i) The DMA controller is initialished by writing the proper control word at the Starting address for the data transfer in the register.
(ii) The mode register is proggram for proper data transfer .
(iii) The appropriate bits are selected to enable the DMA operation.
(iv) When the periferel has the 1st bit of data READ . It sence a DMA request i.e DREQ signal.
(v) The DMA controller sence a whole request i.e HRQ to the processor HOLD pin.
(vi) The processor responce to this input by floating it BUSes and sence HOLD Acknowledge to the DMA controller.
(vii) When the DMA controller receive the HLDA signal it sence out a control signal , disconnect the processor from the buses and connect the DMA controller to the buses.
(viii) When DMA controller gets ontroll of the buses it sence out a memory address from the periferel device is to be written.
(ix) The DMA controller sence a DMA Acknowledge DACK signal To the periferel device.
(x) DMA controller assests both the MEMw and I/O.
(xi) MEMW signal enables the address memory to the accept data written intp it.
(xii) I/O Signal enable to output the data from the disk to the data bus.
(xiii) The byte of data is then transfer dirrectly from the periferel desire to the memory.
(xiv) When the data transfer is connect the DMA controller RESET its HOLD request to the processor release the busses.
(xv) The processor continuties excuted from where it left in the program.
DMA data Transfer scheme :
(i) Burst move of data:
A scheme of DMA data transfer in which the I/O device with draw the DMA request only sfter all the data bytes have been transfer is call Burst move dat transfer. By this technique a block of data is transfered. This technique is employed by magnetic disc drive.
(ii) Cycling stealling:
In this technique a loging block of data transfer by a sequence a DMA circuit .I this method after transfering 1 bytes or several bytes the I/o device withdraw DMA request. This method reduces interference in CPU Activities . The interference can be eliminated by designing at the interfacing transfer only when the CPU is not using the System BUS.